This job is closed and no longer accepting applications. Closed on October 23, 2026.
R&D Engineer
Mountain View, California
FULL_TIME |

Responsible for

  • Validate and sanity check existing FPGA protoyping design on hardware.
  • Migrate and optimize existing FPGA prototyping designs to all Synopsys hardware platforms.
  • Create and edit user documents
  • Work in the lab to conduct hardware experiment including maintaining setups and equipment
  • Responsible for establishing personal timetables according to task assignment and supporting the related assigned project goals of other engineers.

     
    Responsible for

  • Validate and sanity check existing FPGA protoyping design on hardware.
  • Migrate and optimize existing FPGA prototyping designs to all Synopsys hardware platforms.
  • Create and edit user documents
  • Work in the lab to conduct hardware experiment including maintaining setups and equipment
  • Responsible for establishing personal timetables according to task assignment and supporting the related assigned project goals of other engineers.