Join an AI computing hardware team developing chips for probabilistic and thermodynamic computing. You will design critical analog and mixed-signal circuits, taking blocks from architecture through silicon validation as the team advances its next generation of chips.
Design analog and mixed-signal building blocks such as ADCs, PLLs, bandgap references, regulators, oscillators, high-speed dividers, and SerDes.
Own block-level design across multiple chips, from architecture and schematic through layout and tape-out verification, including DRC, ERC, and LVS.
Perform hands-on layout and comprehensive Cadence simulations, including PEX, Monte Carlo, and corner analysis.
Support lab testing and circuit validation using signal generators, spectrum analyzers, and oscilloscopes.
Collaborate with IC, systems, physics, and algorithms teams to bring circuit concepts through to silicon.
Three to six years of CMOS analog and mixed-signal IC design experience, with an MS or PhD in Electrical Engineering focused on analog or mixed-signal design.
Multiple tape-out experiences, ideally in FinFET or 28nm/65nm process nodes.
Experience designing one or more of the listed circuit blocks, along with broad interest in working across circuit types and hands-on tasks.
Strong mixed-signal design skills, practical layout experience, and proficiency with Cadence Virtuoso, PEX, Monte Carlo, and corner analysis.
Ability to perform small-signal and feedback analysis, including closed-loop gain, loading effects, and Miller effects; Python or C experience is useful.
Base salary is $160,000 to $300,000 annually. Visa sponsorship is available.
Hybrid, with three days per week on-site in Boston, Massachusetts, United States.